1. Field of the Invention
The present invention relates to a solid-state imaging device provided with an amplification-type MOS transistor and a method for manufacturing the same and relates to an interline transfer CCD image sensor.
2. Related Background Art
In recent years, attention has been drawn to a solid-state imaging device provided with an amplification-type MOS transistor. In this solid-state imaging device, for each pixel, a signal detected by a photodiode is amplified by a MOS transistor, and the device has a feature of high sensitivity.
FIG. 5 is a circuit diagram showing a configuration of a conventional solid-state imaging device 90. The solid-state imaging device 90 includes a plurality of pixel cells 13 arranged in a matrix form on a semiconductor substrate 14. Each of the pixel cells 13 includes a photodiode 95 that converts incident light into a signal charge and stores the signal charge. In each of the pixel cells 13, a transfer transistor 96 for reading out the signal charge stored in the photodiode 95 is provided.
Each of the pixel cells 13 includes an amplify transistor 12. The amplify transistor 12 amplifies the signal charge read out by the transfer transistor 96. In each of the pixel cells 13, a reset transistor 11 is provided. The reset transistor 11 resets the signal charge read out by the transfer transistor 96.
The solid-state imaging device 90 includes a vertical driving circuit 15. A plurality of reset transistor control lines 111 are connected to the vertical driving circuit 15. The reset transistor control lines 111 are arranged parallel with each other at predetermined intervals and along a horizontal direction so as to be connected to the reset transistors 11 that are respectively provided in the pixel cells 13 arranged along the horizontal direction. A plurality of vertical select transistor control lines 121 further are connected to the vertical driving circuit 15. The vertical select transistor control lines 121 are arranged parallel with each other at predetermined intervals and along the horizontal direction so as to be connected to vertical select transistors that are provided respectively in the pixel cells 13 arranged along the horizontal direction. The vertical select transistor control lines 121 determine a row from which a signal is to be read out.
A source of each vertical select transistor is connected to a vertical signal line 61. A load transistor group 27 is connected to one end of each vertical signal line 61. The other end of each vertical signal line 61 is connected to a row signal storing portion 28. The row signal storing portion 28 includes a switching transistor for capturing signals from one row. A horizontal driving circuit 16 is connected to the row signal storing portion 28.
FIG. 6 is a timing chart for explaining an operation of the conventional solid-state imaging device 90.
When a row selection pulse 101-1 is applied so as to make a level of a vertical select transistor control line 121 high, the vertical select transistors in the selected row turn ON, so that the amplify transistors 12 in the selected row and the load transistor group 27 form a source follower circuit.
While the row selection pulse 101-1 is at a high level, a reset pulse 102-1 for making a reset transistor control line 111 at a high level is applied so as to reset a potential of a floating diffusion layer to which a gate of each of the amplify transistors 12 is connected. Next, while the row selection pulse 101-1 is at the high level, a transfer pulse 103-1 is applied so as to make a level of transfer transistor control lines high, which allows a signal charge stored in each of the photodiodes 95 to be transferred to the floating diffusion layer.
At this time, each of the amplify transistors 12 connected to the floating diffusion layer has a gate voltage equal to the potential of the floating diffusion layer, which allows a voltage that is substantially equal to this gate voltage to appear across the vertical signal line 61. Then, a signal based on the signal charge stored in the photodiode 95 is transferred to the row signal storing portion 28.
Next, the horizontal driving circuit 16 sequentially generates column selection pulses 106-1-1, 106-1-2, . . . so as to extract the signals that have been transferred to the row signal storing portion 28 as an output signal 107-1 corresponding to those obtained from one row.
FIG. 7A is a cross-sectional view showing a configuration of the conventional solid-state imaging device 90, and FIG. 7B schematically shows a change in potential from a photodiode 95 to a transfer transistor 96 that are provided in the conventional solid-state imaging device 90.
The photodiode 95 is a buried-type pnp photodiode that includes a shallow p-type photodiode diffusion layer 99 formed at a surface of a semiconductor substrate 14 and a deep photodiode diffusion layer 98 formed below the shallow p-type photodiode diffusion layer 99 so as to be exposed partially from the surface of the semiconductor substrate 14.
The transfer transistor 96 is formed adjacent to the photodiode 95 and has a gate electrode 97 formed on the semiconductor substrate 14. At a portion of the surface of the semiconductor substrate 14 that is on an opposite side of the photodiode 95 with reference to the transfer transistor 96, a floating diffusion layer 10 is formed. At a portion of the surface of the semiconductor substrate 14 that is on an opposite side of the transfer transistor 96 with reference to the floating diffusion layer 10, a reset transistor 11 is formed so as to have a gate electrode 23. At a portion of the surface of the semiconductor substrate 14 that is on an opposite side of the floating diffusion layer 10 with reference to the reset transistor 11, a power-supply diffusion layer 207 is formed. An element isolation potion 209 is formed at each of the portions on an opposite side of the reset transistor 11 with reference to the power-supply diffusion layer 207 and on an opposite side of the transfer transistor 96 with reference to the photodiode 95.
In a portion of the semiconductor substrate 14 placed below the gate electrode 97 provided in the transfer transistor 96, a threshold value diffusion layer 208 for controlling a channel potential of the transfer transistor 96 is formed adjacent to the deep photodiode diffusion layer 98.
With reference to FIG. 7B, a power-supply voltage of the solid-state imaging device 90 is not less than 10 V. When the gate electrode 23 of the reset transistor 11 is turned ON, a potential of the floating diffusion layer 10 is fixed at the power-supply voltage. Then, when the gate electrode 23 of the reset transistor 11 is turned OFF, the potential of the floating diffusion layer 10 floats electrically.
Next, when the gate electrode 97 of the transfer transistor 96 is turned ON, a signal charge stored in the deep photodiode diffusion layer 98 of the photodiode 95 is introduced to the floating diffusion layer 10 through the threshold value diffusion layer 208 so as to be converted into a signal voltage. The signal voltage allows the modulation of a gate voltage of the amplify transistor 12 shown in FIG. 5 and is extracted to the outside by way of the vertical signal line 61, the row signal storing portion 28 and the horizontal driving circuit 16.
When the signal charge stored in the photodiode 95 is read out, ideally, all of the charge is read out completely so that the remaining signal charge in the photodiode 95 becomes zero. Such an ideal state is referred to as “complete transfer”. The “complete transfer” may include some minor level of residual charge that is a residual state of, for example, about several tens of electrons.
The above-described conventional solid-state imaging device 90 enables the “complete transfer” to be carried out relatively easily, because the gate voltage of the transfer transistor 96 and the power-supply voltage are high at not less than 10 V.
However, in accordance with finer design rules adopted for MOS transistors, the gate voltage of the transfer transistor 96 and the power-supply voltage decrease to about 2.8 to 3.3 V. Therefore, it becomes significantly difficult to carry out the “complete transfer”. The following describes such a problem specifically.
FIG. 7C schematically shows a change in potential from the photodiode 95 to the transfer transistor 96 that are provided in the conventional solid-state imaging device 90.
When the gate voltage of the transfer transistor 96 and the power-supply voltage are about 2.8 to 3.3 V, the potential from the photodiode 95 to the transfer transistor 96 does not change smoothly. The potential from the photodiode 95 to the transfer transistor 96 plunges at a first pocket 17. For instance, the potential does not change smoothly in such a manner that a potential of the first pocket 17 is 2 V, a potential of a barrier 19 is 1.7 V and a potential of a second pocket 18 is 2.1 V. This first pocket 17 occurs at a position 210 that corresponds to an edge of the shallow p-type photodiode diffusion layer 99. A depth of the position 210 where the first pocket 17 occurs is about 0.7 μm.
The potential from the photodiode 95 to the transfer transistor 96 further plunges at the second pocket 18 that is located on a side of the transfer transistor 96 with reference to the first pocket 17. The second pocket 18 occurs at a position 212 that is close to the surface of a portion of the deep photodiode diffusion layer 98 that is not covered with the shallow p-type photodiode diffusion layer 99. A depth of the position 212 where the second pocket 18 occurs is about 0.2 μm or less.
The potential from the photodiode 95 to the transfer transistor 96 has the barrier 19 formed between the first pocket 17 and the second pocket 18. This barrier 19 occurs at a position 211 that is located between the shallow p-type photodiode diffusion layer 99 and the threshold value diffusion layer 208. A depth of the position 211 where the barrier 19 occurs is about 0.4 μm or less.
In this way, when the gate voltage of the transfer transistor 96 and the power-supply voltage decrease to about 2.8 to 3.3 V, the first pocket 17, the second pocket 18 and the barrier 19 are formed. As a result, the potential from the photodiode 95 to the transfer transistor 96 does not change smoothly. For that reason, it becomes significantly difficult to carry out the “complete transfer” of the signal charge stored in the photodiode 95.